Sachin S. Sapatnekar, Sachin S.: search on Z-Library

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1

[IEEE 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Grenoble, France (2020.3.9-2020.3.13)] 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) - GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

Kunal, Kishor, Dhar, Tonmoy, Madhusudan, Meghna, Poojary, Jitesh, Sharma, Arvind, Xu, Wenbin, Burns, Steven M., Hu, Jiang, Harjani, Ramesh, Sapatnekar, Sachin S.

Year:

2020

File:

PDF, 1.32 MB

2020

2

[IEEE 2011 IEEE Custom Integrated Circuits Conference - CICC 2011 - San Jose, CA, USA (2011.09.19-2011.09.21)] 2011 IEEE Custom Integrated Circuits Conference (CICC) - Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network

Zhou, Pingqiang, Jiao, Dong, Kim, Chris H., Sapatnekar, Sachin S.

Year:

2011

Language:

english

File:

PDF, 448 KB

english, 2011

3

[IEEE 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Singapore, Singapore (2013.11.11-2013.11.13)] 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities

Paul, Ayan, Jiao, Dong, Sapatnekar, Sachin, Kim, Chris H.

Year:

2013

Language:

english

File:

PDF, 578 KB

english, 2013

4

The Impact of BTI Variations on Timing in Digital Logic Circuits

Fang, Jianxin, Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2013

Language:

english

File:

PDF, 829 KB

english, 2013

5

[IEEE 2012 IEEE Custom Integrated Circuits Conference - CICC 2012 - San Jose, CA, USA (2012.09.9-2012.09.12)] Proceedings of the IEEE 2012 Custom Integrated Circuits Conference - Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Paul, Ayan, Amrein, Matt, Gupta, Saket, Vinod, Arvind, Arun, Abhishek, Sapatnekar, Sachin, Kim, Chris H.

Year:

2012

Language:

english

File:

PDF, 1.45 MB

english, 2012

6

Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor

Jongyeon Kim,, Paul, Ayan, Crowell, Paul A., Koester, Steven J., Sapatnekar, Sachin S., Jian-Ping Wang,, Kim, Chris H.

Journal:

Proceedings of the IEEE

Year:

2015

Language:

english

File:

PDF, 5.24 MB

english, 2015

7

[IEEE 2010 11th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2010.03.22-2010.03.24)] 2010 11th International Symposium on Quality Electronic Design (ISQED) - Scalable methods for the analysis and optimization of gate oxide breakdown

Jianxin Fang,, Sapatnekar, Sachin S.

Year:

2010

Language:

english

File:

PDF, 251 KB

english, 2010

8

[Integrated Circuits and Systems] Three Dimensional Integrated Circuit Design || Thermal and Power Delivery Challenges in 3D ICs

Xie, Yuan, Cong, Jason, Sapatnekar, Sachin

Year:

2010

Language:

english

File:

PDF, 1.06 MB

english, 2010

9

[ACM Press the 54th Annual Design Automation Conference 2017 - Austin, TX, USA (2017.06.18-2017.06.22)] Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17 - A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

Wang, Jian-Ping, Niemier, Michael, Naeemi, Azad, Chien, Chia-Ling, Ross, Caroline, Kawakami, Roland, Sapatnekar, Sachin S., Kim, Chris H., Crowell, Paul, Koester, Steve, Datta, Supriyo, Roy, Kaushik,

Year:

2017

Language:

english

File:

PDF, 1.43 MB

english, 2017

10

A Simple Yet Efficient Accuracy-Configurable Adder Design

Xu, Wenbin, Sapatnekar, Sachin S., Hu, Jiang

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 8.41 MB

english, 2018

11

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping

Zabihi, Masoud, Chowdhury, Zamshed, Zhao, Zhengyang, Karpuzcu, Ulya R., Wang, Jian-Ping, Sapatnekar, Sachin

Journal:

IEEE Transactions on Computers

Year:

2018

Language:

english

File:

PDF, 9.37 MB

english, 2018

12

[IEEE 2019 20th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2019.3.6-2019.3.7)] 20th International Symposium on Quality Electronic Design (ISQED) - Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs

Chhabria, Vidya A., Sapatnekar, Sachin S.

Year:

2019

Language:

english

File:

PDF, 1.60 MB

english, 2019

13

[ACM Press the 56th Annual Design Automation Conference 2019 - Las Vegas, NV, USA (2019.06.02-2019.06.06)] Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19 - Toward an Open-Source Digital Flow

Ajayi, Tutu, Neseem, Marina, Pradipta, Geraldo, Reda, Sherief, Saligane, Mehdi, Sapatnekar, Sachin S., Sechen, Carl, Shalan, Mohamed, Swartz, William, Wang, Lutong, Wang, Zhehong, Chhabria, Vidya A.,

Year:

2019

File:

PDF, 381 KB

2019

14

[IEEE 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) - Beijing, China (2020.1.13-2020.1.16)] 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) - Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques

Chhabria, Vidya A., Kahng, Andrew B., Kim, Minsoo, Mallappa, Uday, Sapatnekar, Sachin S., Xu, Bangqi

Year:

2020

File:

PDF, 1.12 MB

2020

15

A survey on multi-net global routing for integrated circuits

Jiang Hu, Sachin S. Sapatnekar

Journal:

Integration, the VLSI Journal

Year:

2001

Language:

english

File:

PDF, 472 KB

english, 2001

16

Probability-driven routing in a datapath environment

Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert

Journal:

Integration, the VLSI Journal

Year:

2002

Language:

english

File:

PDF, 557 KB

english, 2002

17

Buffering global interconnects in structured ASIC design

Tianpei Zhang, Sachin S. Sapatnekar

Journal:

Integration, the VLSI Journal

Year:

2008

Language:

english

File:

PDF, 529 KB

english, 2008

18

Retiming control logic

Naresh Maheshwari, Sachin S. Sapatnekar

Journal:

Integration, the VLSI Journal

Year:

1999

Language:

english

File:

PDF, 301 KB

english, 1999

19

[IEEE ISLPED'06 2006 International Symposium on Low Power Electronics and Design - Tegernsee, Germany (2006.10.4-2006.10.6)] ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design - Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis

Nookala, Vidyasagar, Lilja, David J., Sapatnekar, Sachin S.

Year:

2006

Language:

english

File:

PDF, 4.72 MB

english, 2006

20

Stochastic Preconditioning for Diagonally Dominant Matrices

Qian, Haifeng, Sapatnekar, Sachin S.

Journal:

SIAM Journal on Scientific Computing

Year:

2008

Language:

english

File:

PDF, 410 KB

english, 2008

21

Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]

Sapatnekar, Sachin

Journal:

IEEE Design & Test of Computers

Year:

2008

Language:

english

File:

PDF, 244 KB

english, 2008

22

Building your yield of dreams [review of Design for Manufacturability and Yield for Nano-Scale CMOS by Charles Chiang and Jamil Kawa; 2007]

Sapatnekar, Sachin

Journal:

IEEE Design & Test of Computers

Year:

2008

Language:

english

File:

PDF, 365 KB

english, 2008

23

[ACM Press the International Conference - San Jose, California (2012.11.05-2012.11.08)] Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 - Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications

Zhou, Pingqiang, Choi, Won Ho, Kim, Bongjin, Kim, Chris H., Sapatnekar, Sachin S.

Year:

2012

Language:

english

File:

PDF, 702 KB

english, 2012

24

[Integrated Circuits and Systems] Three Dimensional Integrated Circuit Design ||

Xie, Yuan, Cong, Jason, Sapatnekar, Sachin

Year:

2010

Language:

english

File:

PDF, 8.58 MB

english, 2010

25

Distributed On-Chip Switched-Capacitor DC–DC Converters Supporting DVFS in Multicore Systems

Zhou, Pingqiang, Paul, Ayan, Kim, Chris H., Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.77 MB

english, 2014

26

[ACM Press the 45th annual conference - Anaheim, California (2008.06.08-2008.06.13)] Proceedings of the 45th annual conference on Design automation - DAC '08 - Reinventing EDA with manycore processors

Sapatnekar, Sachin, Haritan, Eshel, Keutzer, Kurt, Devgan, Anirudh, Kirkpatrick, Desmond A., Meier, Stephen, Pryor, Duaine, Spyrou, Tom

Year:

2008

Language:

english

File:

PDF, 150 KB

english, 2008

27

[Integrated Circuits and Systems] Three Dimensional Integrated Circuit Design || Thermal Via Insertion and Thermally Aware Routing in 3D ICs

Xie, Yuan, Cong, Jason, Sapatnekar, Sachin

Year:

2010

Language:

english

File:

PDF, 823 KB

english, 2010

28

[ACM Press the 2002 international symposium - San Diego, CA, USA (2002.04.07-2002.04.10)] Proceedings of the 2002 international symposium on Physical design - ISPD '02 - An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Su, Haihua, Sapatnekar, Sachin S., Nassif, Sani R.

Year:

2002

Language:

english

File:

PDF, 238 KB

english, 2002

29

[ACM Press the International Conference - San Jose, California (2012.11.05-2012.11.08)] Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 - Circuit reliability

Fang, Jianxin, Gupta, Saket, Kumar, Sanjay V., Marella, Sravan K., Mishra, Vivek, Zhou, Pingqiang, Sapatnekar, Sachin S.

Year:

2012

Language:

english

File:

PDF, 743 KB

english, 2012

30

Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits

Fang, Jianxin, Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.40 MB

english, 2014

31

Variation-Aware Variable Latency Design

Gupta, Saket, Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.62 MB

english, 2014

32

[IEEE 1994 International Conference on Parallel Processing (ICPP'94) - North Carolina State University, NC, USA (1994.08.15-1994.08.19)] 1994 International Conference on Parallel Processing (ICPP'94) - A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers

Ramaswamy, Shankar, Sapatnekar, Sachin, Banerjee, Prithviraj

Year:

1994

Language:

english

File:

PDF, 632 KB

english, 1994

33

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property

Gu, Jie, Keane, John, Sapatnekar, Sachin, Kim, Chris H.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2008

Language:

english

File:

PDF, 427 KB

english, 2008

34

[IEEE IEEE Custom Integrated Circuits Conference 2006 - San Jose, CA, USA (2006.09.10-2006.09.13)] IEEE Custom Integrated Circuits Conference 2006 - Width Quantization Aware FinFET Circuit Design

Gu, Jie, Keane, John, Sapatnekar, Sachin, Kim, Chris

Year:

2006

Language:

english

File:

PDF, 1.34 MB

english, 2006

35

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Kumar, Sanjay V., Kim, Chris H., Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2011

Language:

english

File:

PDF, 1.10 MB

english, 2011

36

[IEEE 2007 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA (2007.11.4-2007.11.8)] 2007 IEEE/ACM International Conference on Computer-Aided Design - A general model for performance optimization of sequential systems

Bufistov, Dmitry, Cortadella, Jord, Kishinevsky, Mike, Sapatnekar, Sachin

Year:

2007

Language:

english

File:

PDF, 663 KB

english, 2007

37

[IEEE 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - San Jose, CA, USA (2013.11.18-2013.11.21)] 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - The impact of shallow trench isolation effects on circuit performance

Marella, Sravan K., Sapatnekar, Sachin S.

Year:

2013

Language:

english

File:

PDF, 742 KB

english, 2013

38

[IEEE 2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011 - Yokohama, Japan (2011.01.25-2011.01.28)] 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) - Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability

Fang, Jianxin, Sapatnekar, Sachin S.

Year:

2011

Language:

english

File:

PDF, 196 KB

english, 2011

39

[IEEE 2006 IEEE/ACM International Conference on Computer Aided Design - Double Tree Hotel, San Jose, CA,USA (2006.11.5-2006.11.9)] 2006 IEEE/ACM International Conference on Computer Aided Design - An Analytical Model for Negative Bias Temperature Instability

Kumar, Sanjay, Kim, Chris, Sapatnekar, Sachin

Year:

2006

Language:

english

File:

PDF, 2.78 MB

english, 2006

40

[IEEE 2014 27th International Conference on VLSI Design - India (2014.01.5-2014.01.9)] 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems - Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations

Paul, Ayan, Kshirsagar, Chaitanya, Sapatnekar, Sachin S., Koester, Steven, Kim, Chris H.

Year:

2014

File:

PDF, 391 KB

2014

41

[IEEE 2014 27th International Conference on VLSI Design - India (2014.01.5-2014.01.9)] 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems - Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations

Paul, Ayan, Kshirsagar, Chaitanya, Sapatnekar, Sachin S., Koester, Steven, Kim, Chris H.

Year:

2014

Language:

english

File:

PDF, 391 KB

english, 2014

42

[IEEE 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore (2014.01.20-2014.01.23)] 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Predicting circuit aging using ring oscillators

Sengupta, Deepashree, Sapatnekar, Sachin S.

Year:

2014

Language:

english

File:

PDF, 216 KB

english, 2014

43

[IEEE 2007 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA (2007.11.4-2007.11.8)] 2007 IEEE/ACM International Conference on Computer-Aided Design - Module assignment for pin-limited designs under the stacked-Vdd paradigm

Yong Zhan,, Tianpei Zhang,, Sapatnekar, Sachin S.

Year:

2007

Language:

english

File:

PDF, 549 KB

english, 2007

44

[IEEE 2009 Asia and South Pacific Design Automation Conference (ASP-DAC) - Yokohama, Japan (2009.01.19-2009.01.22)] 2009 Asia and South Pacific Design Automation Conference - Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar, Sanjay V., Kim, Chris H., Sapatnekar, Sachin S.

Year:

2009

Language:

english

File:

PDF, 212 KB

english, 2009

45

[IEEE 2009 Asia and South Pacific Design Automation Conference (ASP-DAC) - Yokohama, Japan (2009.01.19-2009.01.22)] 2009 Asia and South Pacific Design Automation Conference - Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Zhou, Pingqiang, Sridharan, Karthikk, Sapatnekar, Sachin S.

Year:

2009

Language:

english

File:

PDF, 269 KB

english, 2009

46

[IEEE 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC) - Sydney, Australia (2012.01.30-2012.02.2)] 17th Asia and South Pacific Design Automation Conference - GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation

Gupta, Saket, Sapatnekar, Sachin S.

Year:

2012

Language:

english

File:

PDF, 373 KB

english, 2012

47

[IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Understanding the impact of transistor-level BTI variability

Fang, Jianxin, Sapatnekar, Sachin S.

Year:

2012

Language:

english

File:

PDF, 544 KB

english, 2012

48

[IEEE 2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010 - Taipei, Taiwan (2010.01.18-2010.01.21)] 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) - Application-specific 3D Network-on-Chip design using simulated allocation

Pingqiang Zhou,, Ping-Hung Yuh,, Sapatnekar, Sachin S.

Year:

2010

Language:

english

File:

PDF, 161 KB

english, 2010

49

Process and Reliability Sensors for Nanoscale CMOS

Keane, John P., Kim, Chris H., Liu, Qunzeng, Sapatnekar, Sachin S.

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 849 KB

english, 2012

50

[IEEE 2011 International Symposium on Low Power Electronics and Design (ISLPED) - Fukuoka, Japan (2011.08.1-2011.08.3)] IEEE/ACM International Symposium on Low Power Electronics and Design - NoC frequency scaling with flexible-pipeline routers

Zhou, Pingqiang, Yin, Jieming, Zhai, Antonia, Sapatnekar, Sachin S.

Year:

2011

Language:

english

File:

PDF, 796 KB

english, 2011